//------------------------------------------------------------------------------
// Copyright (c) 2012 by Silicon Laboratories.
// All rights reserved. This program and the accompanying materials
// are made available under the terms of the Silicon Laboratories End User
// License Agreement which accompanies this distribution, and is available at
// http://developer.silabs.com/legal/version/v10/License_Agreement_v10.htm
// Original content and implementation provided by Silicon Laboratories.
//------------------------------------------------------------------------------

//==============================================================================
// WARNING:
//
// This file is auto-generated by AppBuilder and should not be modified.
// Any hand modifications will be lost if the project is regenerated.
//==============================================================================
// library
// hal
#include "gPB.h"

#include <SI32_PBCFG_A_Type.h>
#include <si32_device.h>
#include <SI32_PBSTD_A_Type.h>
#include <SI32_PBGP_A_Type.h> //I dont know why, but in SPI1 it was included...
#include <SI32_CLKCTRL_A_Type.h>
// application


//==============================================================================
//CONFIGURATION FUNCTIONS
//==============================================================================
void gPB_enter_off_config()
{
   // ALL PORTS HI-Z
   SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_0, 0x0000FFFF);
   SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_1, 0x0000FFFF);
   SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_2, 0x0000FFFF);
   SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_3, 0x00007FFF);

   // DISABLE CROSSBARS
   SI32_PBCFG_A_disable_crossbar_0(SI32_PBCFG_0);

}

//------------------------------------------------------------------------------
// Sets up ports for all peripherals
// NOTE 'default' refers to the default device setup for the application.
void gPB_enter_default_config()
{
   // START APB CLK AND ENABLE SW PRINF
   SI32_CLKCTRL_A_enable_apb_to_modules_0(SI32_CLKCTRL_0,
                                                   SI32_CLKCTRL_A_APBCLKG0_PB0|
                                                   SI32_CLKCTRL_A_APBCLKG0_SPI1|
                                                   SI32_CLKCTRL_A_APBCLKG0_FLASHCTRL0);

   SI32_PBCFG_A_disable_jtag(SI32_PBCFG_0);

   // ENABLE LED DRIVERS (P1.4, P1.5)
   SI32_PBSTD_A_set_pins_push_pull_output(SI32_PBSTD_1, 0x00000030);

   // UART PINS TO PROPER CONFIG (TX = PB1.2, RX = PB1.3)
   SI32_PBSTD_A_set_pins_push_pull_output(SI32_PBSTD_1, 0x0000004);
   SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_1, 0x00000008);

   SI32_PBSTD_A_write_pbskipen(SI32_PBSTD_1, 0x0000000C);

 //for SPI1
   SI32_PBSTD_A_write_pbskipen(SI32_PBSTD_2, 0x000000F0);
  SI32_PBCFG_A_enable_spi1_on_crossbar(SI32_PBCFG_0);
  // PB2 Setup it could be necessary because of SPI1 pins (if for UART pins the above skippens are necessary..)
  SI32_PBSTD_A_set_pins_digital_input(SI32_PBSTD_2, 0x00000021); //az egyes a végén a PB2.0 IRQ bemenetet jelzi
  SI32_PBSTD_A_set_pins_push_pull_output(SI32_PBSTD_2, 0x000000D2);

  // ENABLE CROSSBAR 0 & 1. WE WILL DRIVE LED's ON CROSSBAR 1 and UART on 0
  SI32_PBCFG_A_enable_crossbar_0(SI32_PBCFG_0);

}

//---eof------------------------------------------------------------------------
